Signal integrity analysis of high - speed digital circuit 高速數(shù)字電路的信號(hào)完整性分析
Signal integrity analysis in high speed design 高速電路的信號(hào)完整性分析
A new signal integrity analysis technology in high speed computer system 一種新的高速計(jì)算機(jī)信號(hào)完整性分析技術(shù)
The 4th chapter is the emphasis of this dissertation , with its content of schematic , signal integrity analysis and high speed pcb design 第四章硬件設(shè)計(jì)是本論文的重點(diǎn),主要從原理圖、信號(hào)完整性分析、高速pcb設(shè)計(jì)三個(gè)方面詳細(xì)闡述。
The dissertation presents an automatic flow to characterize and model cells accurately and quickly by the stimulus reduction algorithm , the input signal driving algorithm , the characterization point dynamic insertion algorithm , the result table optimization algorithm and input signal integrity analysis algorithm , which reaches the advanced level in this field 本文給出了深亞微米工藝條件下單元工藝參數(shù)提取和建模的完整流程,該流程能快速精確地完成單元工藝參數(shù)提取和建模。文中提出的激勵(lì)波形約簡(jiǎn)算法、輸入信號(hào)驅(qū)動(dòng)算法、測(cè)試點(diǎn)動(dòng)態(tài)插入算法和結(jié)果表優(yōu)化壓縮算法等,達(dá)到了國際同類研究的先進(jìn)水平。